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oval:org.secpod.oval:def:61189
A microarchitectural timing flaw was found on some Intel processors. In a corner case where data in-flight during the eviction process can end up in the fill buffers and not properly cleared by the MDS mitigations. The fill buffer contents (which were expected to be blank) can be inferred using MDS ... oval:org.secpod.oval:def:61109 Cleanup errors in some data cache evictions for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. oval:org.secpod.oval:def:1601157 A new domain bypass transient execution attack known as Special Register Buffer Data Sampling has been found. This flaw allows data values from special internal registers to be leaked by an attacker able to execute code on any core of the CPU. An unprivileged, local attacker can use this flaw to in ... oval:org.secpod.oval:def:89050379 This update for ucode-intel fixes the following issues: Updated Intel CPU Microcode to 20200602 This update contains security mitigations for: - CVE-2020-0543: Fixed a side channel attack against special registers which could have resulted in leaking of read values to cores other than the one whic ... oval:org.secpod.oval:def:205881 The microcode_ctl packages provide microcode updates for Intel. Security Fix: * hw: Special Register Buffer Data Sampling * hw: Vector Register Data Sampling * hw: L1D Cache Eviction Sampling * hw: vt-d related privilege escalation * hw: improper isolation of shared resources in some Intel Proc ... oval:org.secpod.oval:def:506283 The microcode_ctl packages provide microcode updates for Intel. Security Fix: * hw: Special Register Buffer Data Sampling * hw: Vector Register Data Sampling * hw: L1D Cache Eviction Sampling * hw: vt-d related privilege escalation * hw: improper isolation of shared resources in some Intel Proc ... oval:org.secpod.oval:def:506284 The microcode_ctl packages provide microcode updates for Intel. Security Fix: * hw: Special Register Buffer Data Sampling * hw: Vector Register Data Sampling * hw: L1D Cache Eviction Sampling * hw: vt-d related privilege escalation * hw: improper isolation of shared resources in some Intel Proc ... oval:org.secpod.oval:def:89002922 This update for ucode-intel fixes the following issues: Updated Intel CPU Microcode to 20200602 This update contains security mitigations for: - CVE-2020-0543: Fixed a side channel attack against special registers which could have resulted in leaking of read values to cores other than the one whic ... oval:org.secpod.oval:def:604884 This update ships updated CPU microcode for some types of Intel CPUs and provides mitigations for the Special Register Buffer Data Sampling , Vector Register Sampling and L1D Eviction Sampling hardware vulnerabilities. The microcode update for HEDT and Xeon CPUs with signature 0x50654 which was re ... oval:org.secpod.oval:def:705506 intel-microcode: Processor microcode for Intel CPUs Several security issues were fixed in Intel Microcode. oval:org.secpod.oval:def:4501386 The microcode_ctl packages provide microcode updates for Intel. Security Fix: * hw: Special Register Buffer Data Sampling * hw: Vector Register Data Sampling * hw: L1D Cache Eviction Sampling * hw: vt-d related privilege escalation * hw: improper isolation of shared resources in some Intel Proc ... oval:org.secpod.oval:def:1502941 The advisory is missing the security advisory description. For more information please visit the reference link oval:org.secpod.oval:def:1502952 The advisory is missing the security advisory description. For more information please visit the reference link oval:org.secpod.oval:def:1502954 The advisory is missing the security advisory description. For more information please visit the reference link oval:org.secpod.oval:def:74585 The microcode_ctl packages provide microcode updates for Intel. Security Fix: * hw: Special Register Buffer Data Sampling * hw: Vector Register Data Sampling * hw: L1D Cache Eviction Sampling * hw: vt-d related privilege escalation * hw: improper isolation of shared resources in some Intel Proc ... oval:org.secpod.oval:def:205580 Security Fix: * hw: Special Register Buffer Data Sampling * hw: L1D Cache Eviction Sampling * hw: Vector Register Data Sampling For more details about the security issue, including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page listed in the Refer ... oval:org.secpod.oval:def:205578 The microcode_ctl packages provide microcode updates for Intel and AMD processors. Security Fix: * hw: Special Register Buffer Data Sampling * hw: L1D Cache Eviction Sampling * hw: Vector Register Data Sampling For more details about the security issue, including the impact, a CVSS score, acknow ... oval:org.secpod.oval:def:1700351 A new domain bypass transient execution attack known as Special Register Buffer Data Sampling has been found. This flaw allows data values from special internal registers to be leaked by an attacker able to execute code on any core of the CPU. An unprivileged, local attacker can use this flaw to in ... oval:org.secpod.oval:def:89002977 This update for ucode-intel fixes the following issues: Updated Intel CPU Microcode to 20200602 This update contains security mitigations for: - CVE-2020-0543: Fixed a side channel attack against special registers which could have resulted in leaking of read values to cores other than the one whic ... oval:org.secpod.oval:def:2500455 The microcode_ctl packages provide microcode updates for Intel. oval:org.secpod.oval:def:64128 intel-microcode: Processor microcode for Intel CPUs Several security issues were fixed in Intel Microcode. oval:org.secpod.oval:def:89000164 This update for microcode_ctl fixes the following issues: Updated Intel CPU Microcode to 20200602 This update contains security mitigations for: - CVE-2020-0543: Fixed a side channel attack against special registers which could have resulted in leaking of read values to cores other than the one wh ... oval:org.secpod.oval:def:1505045 [4:20210216-1.20210608.0.1] - add support for UEK6 kernels - enable early update for 06-4f-01 - remove no longer appropriate caveats for 06-2d-07 and 06-55-04 - enable early and late load on RHCK [4:20210216-1.20210608.1] - Update Intel CPU microcode to microcode-20210608 release: - Fixes in release ... oval:org.secpod.oval:def:503775 Security Fix: * hw: Special Register Buffer Data Sampling * hw: L1D Cache Eviction Sampling * hw: Vector Register Data Sampling For more details about the security issue, including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page listed in the Refer ... oval:org.secpod.oval:def:503774 The microcode_ctl packages provide microcode updates for Intel and AMD processors. Security Fix: * hw: Special Register Buffer Data Sampling * hw: L1D Cache Eviction Sampling * hw: Vector Register Data Sampling For more details about the security issue, including the impact, a CVSS score, acknow ... oval:org.secpod.oval:def:503777 Security Fix: * hw: Special Register Buffer Data Sampling * hw: L1D Cache Eviction Sampling * hw: Vector Register Data Sampling For more details about the security issue, including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page listed in the Refer ... oval:org.secpod.oval:def:1505046 [2:2.1-73.11.0.1] - for Intel, do not trigger load if on-disk microcode is not an update [Orabug: 30634727] - set early_microcode=no in virtualized guests to avoid early load bugs [Orabug: 30618736] - ensure late loading fixes are present on 4.1.12-* and 4.14.35-* - enable early and late load for 5. ... oval:org.secpod.oval:def:64154 This update ships updated CPU microcode for some types of Intel CPUs and provides mitigations for the Special Register Buffer Data Sampling , Vector Register Sampling and L1D Eviction Sampling hardware vulnerabilities. The microcode update for HEDT and Xeon CPUs with signature 0x50654 which was re ... |
